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ISL84541, ISL84542, ISL84543, ISL84544
Data Sheet September 2003 FN6016.6
Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches
The Intersil ISL84541-ISL84544 devices are precision, dual analog switches designed to operate from a single +2.7V to +12V supply. Targeted applications include battery powered equipment that benefit from the devices' low power consumption (5W), low leakage currents (100pA max), and fast switching speeds (tON = 35ns, tOFF = 25ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to "mux-in" additional functionality while reducing ASIC design risk. Some of the smallest packages are available alleviating board space limitations, and making Intersil's newest line of low-voltage switches an ideal solution. The ISL84541/ISL84542/ISL84543 are dual singlepole/single-throw (SPST) devices. The ISL84541 has two normally open (NO) switches; the ISL84542 has two normally closed (NC) switches; the ISL84543 has one NO and one NC switch and can be used as an SPDT. The ISL84544 is a committed SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions, see the ISL43120 - 22 and ISL43210 datasheet.
TABLE 1. FEATURES AT A GLANCE ISL84541 NUMBER OF SWITCHES SW 1 / SW 2 3.3V RON 3.3V tON / tOFF 5V RON 5V tON / tOFF PACKAGES 2 NO / NO 50 50 / 20ns 30 35 / 25ns 8 Ld PDIP, 8 Ld SOIC, 8 Ld SOT-23, 8 Ld MSOP ISL84542 ISL84543 2 NC / NC 50 2 NO / NC 50 ISL84544 1 SPDT 50 50 / 20ns 30 35 / 25ns 8 Ld PDIP, 8 Ld SOIC, 6 Ld SOT-23
Features
* Pb-free Available as an Option * Drop-in Replacements for MAX4541 - MAX4544, DG9461, DG9262 - DG9263 * Fully Specified at 3.3V and 5V Supplies * Pin Compatible with MAX323 - MAX325 * ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 30 * RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1 * Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +12V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<5W * Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA * Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns * Guaranteed Break-Before-Make (ISL84543/ISL84544 only) * Minimum 2000V ESD Protection per Method 3015.7 * TTL, CMOS Compatible * Available in SOT-23 Packaging
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Communications Systems - Military Radios - PBX, PABX * Test Equipment - Ultrasound - Electrocardiograph * Heads-Up Displays * Audio and Video Switching * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
50 / 20ns 50 / 20ns 30 30
35 / 25ns 35 / 25ns 8 Ld PDIP, 8 Ld SOIC, 8 Ld SOT-23
Related Literature
Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84541, ISL84542, ISL84543, ISL84544 Pinouts
(Note 1) ISL84541 (PDIP, SOIC, MSOP) TOP VIEW
NO1 1 COM1 2 IN2 3 GND 4 8 V+ 7 IN1 6 COM2 5 NO2
ISL84541 (SOT-23) TOP VIEW
NO1 1 V+ 2 IN2 3 COM2 4 8 COM1 7 IN1 6 GND 5 NO2
ISL84542 (PDIP, SOIC) TOP VIEW
ISL84542 (SOT-23) TOP VIEW
NC1 1 COM1 2 IN2 3 GND 4
8 V+ 7 IN1 6 COM2 5 NC2
NC1 1 V+ 2 IN2 3 COM2 4
8 COM1 7 IN1 6 GND 5 NC2
ISL84543 (PDIP, SOIC) TOP VIEW
NO1 1 COM1 2 IN2 3 GND 4 8 V+ 7 IN1 6 COM2 5 NC2
ISL84543 (SOT-23) TOP VIEW
NO1 1 V+ 2 IN2 3 COM2 4 8 COM1 7 IN1 6 GND 5 NC2
ISL84544 (PDIP, SOIC) TOP VIEW
NO 1 COM 2 NC 3 GND 4 8 V+ 7 IN 6 NC 5 NC
ISL84544 (SOT-23) TOP VIEW
IN 1 V+ 2 GND 3
6 NO 5 COM 4 NC
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
ISL84541 ISL84542 LOGIC 0 1 NOTE: SW 1, 2 OFF ON SW 1, 2 ON OFF ISL84543 SW 1 OFF ON SW 2 ON OFF ISL84544 PIN NC PIN NO ON OFF OFF ON
Pin Descriptions
PIN V+ GND IN COM NO NC N.C. FUNCTION System Power Supply Input (+2.7V to +12V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin No Internal Connection
Logic "0" 0.8V. Logic "1" 2.4V.
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ISL84541, ISL84542, ISL84543, ISL84544 Ordering Information
PART NO. (BRAND) ISL84541CP ISL84541CPZ (See Note 2) ISL84541CB ISL84541CB-T ISL84541CBZ (See Note 2) ISL84541CBZ-T (See Note 2) ISL84541IP ISL84541IPZ (See Note 2) ISL84541IB ISL84541IB-T ISL84541IBZ (See Note 2) ISL84541IBZ-T (See Note 2) ISL84541IH-T (541I) TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC PKG. DWG. # E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 P8.064 P8.064 M8.118 M8.118 M8.118 M8.118 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 P8.064
Ordering Information
PART NO. (BRAND) TEMP. RANGE (oC) PACKAGE PKG. DWG. # P8.064 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 P8.064 P8.064 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15 M8.15 M8.15 M8.15 P6.064 P6.064
ISL84542IHZ-T 8 Ld SOT-23 Tape and Reel (542I) (See Note 2) (Pb-free) ISL84543CP ISL84543CPZ (See Note 2) ISL84543CB ISL84543CB-T ISL84543CBZ (See Note 2) ISL84543CBZ-T (See Note 2) ISL84543IP ISL84543IPZ (See Note 2) ISL84543IB ISL84543IB-T ISL84543IBZ (See Note 2) ISL84543IBZ-T (See Note 2) ISL84543IH-T (543I) 0 to 70 0 to 70 0 to 70 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel 0 to 70 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel 0 to 70 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel -40 to 85 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel -40 to 85 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) 8 Ld SOT-23 Tape and Reel
8 Ld SOIC Tape and Reel (Pb-free) 8 Ld SOT-23 Tape and Reel
ISL84541IHZ-T 8 Ld SOT-23 Tape and Reel (541I) (See Note 2) (Pb-free) ISL84541IU (541I) ISL84541IU-T (541I) ISL84541IUZ (541I) (See Note 2) -40 to 85 8 Ld MSOP
8 Ld MSOP Tape and Reel -40 to 85 8 Ld MSOP (Pb-free)
ISL84543IHZ-T 8 Ld SOT-23 Tape and Reel (543I) (See Note 2) (Pb-free) ISL84544CP ISL84544CPZ (See Note 2) ISL84544CB ISL84544CB-T ISL84544CBZ (See Note 2) ISL84544CBZ-T (See Note 2) ISL84544IP ISL84544IPZ (See Note 2) ISL84544IB ISL84544IB-T ISL84544IBZ (See Note 2) ISL84544IBZ-T (See Note 2) ISL84544IH-T (544I) 0 to 70 0 to 70 0 to 70 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
ISL84541IUZ-T 8 Ld MSOP Tape and Reel (541I) (See Note 2) (Pb-free) ISL84542CP ISL84542CPZ (See Note 2) ISL84542CB ISL84542CB-T ISL84542CBZ (See Note 2) ISL84542CBZ-T (See Note 2) ISL84542IP ISL84542IPZ (See Note 2) ISL84542IB ISL84542IB-T ISL84542IBZ (See Note 2) ISL84542IBZ-T (See Note 2) ISL84542IH-T (542I) 0 to 70 0 to 70 0 to 70 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel 0 to 70 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel 0 to 70 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) -40 to 85 -40 to 85 -40 to 85 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC
8 Ld SOIC Tape and Reel -40 to 85 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) 6 Ld SOT-23 Tape and Reel
8 Ld SOIC Tape and Reel -40 to 85 8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel (Pb-free) 8 Ld SOT-23 Tape and Reel
ISL84544IHZ-T 6 Ld SOT-23 Tape and Reel (544I) (See Note 2) (Pb-free)
NOTE: 2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
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ISL84541, ISL84542, ISL84543, ISL84544
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages IN (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 3) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 215 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 210 8 LD SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 LD PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Other Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC, MSOP and SOT-23 - Lead Tips Only)
Operating Conditions
Temperature Range ISL8454XCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ISL8454XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEMP (oC) MIN (NOTE 6) MAX (NOTE 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
TEST CONDITIONS
TYP
Full V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 25 Full
0 -0.1 -5 -0.1 -5 -0.2 -10
30 0.8 7 0.01 -
V+ 60 75 2 4 8 0.1 5 0.1 5 0.2 10
V nA nA nA nA nA nA
RON Matching Between Channels, RON
V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3.5V
25 Full
RON Flatness, RFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF)
V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 7
Full 25 Full
COM OFF Leakage Current, ICOM(OFF)
V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, Note 7
25 Full
COM ON Leakage Current, ICOM(ON)
V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating, Note 7
25 Full
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ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEMP (oC) MIN (NOTE 6) MAX (NOTE 6) UNITS
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON
TEST CONDITIONS
TYP
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V, See Figure 1
25 Full
2
35 25 10
100 240 75 150 -
ns ns ns ns ns
Turn-OFF Time, tOFF
VNO or VNC = 3V, RL =1k, CL = 35pF, VIN = 0 to 3V, See Figure 1
25 Full
Break-Before-Make Time Delay (ISL84543, ISL84544), tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
RL = 300, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V, See Figure 3 CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 1MHz, See Figure 4 RL = 50, CL = 5pF, f = 1MHz, See Figure 6
Full
25 25 25 25 25
-
1 76 -90 8 8
5 -
pC dB dB pF pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7
f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7, ISL84541/2/3 f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7, ISL84544
25
-
13
-
pF
25
-
20
-
pF
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off Full Full 2.7 -1 0.0001 12 1 V A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH NOTES: 5. VIN = input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. Full Full 2.4 0.8 V V
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ISL84541, ISL84542, ISL84543, ISL84544
Electrical Specifications - 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEMP (oC) MIN (NOTE 6) MAX (NOTE 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
TEST CONDITIONS
TYP
Full V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V 25 Full
0 -0.1 -5 -0.1 -5 -0.2 -10
50 0.8 6 7 0.01 0.01 -
V+ 80 140 2 4 10 12 0.1 5 0.1 5 0.2 10
V nA nA nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V
25 Full
V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, Note 7
25 Full
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
25 Full
V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, Note 7
25 Full
V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating, Note 7
25 Full
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
25 Full
-
50
120 200
ns ns ns ns ns
Turn-OFF Time, tOFF
VNO or VNC = 1.5V, RL =1k, CL = 35pF, VIN = 0 to 3V
25 Full
3
20 30
50 120 -
Break-Before-Make Time Delay (ISL84543, ISL84544), tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
RL = 300, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3V CL = 1.0nF, VG = 0V, RG = 0 RL = 50, CL = 5pF, f = 1MHz
Full
25 25 25 25 25
-
1 76 -90 8 8
5 -
pC dB dB pF pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V f = 1MHz, VNO or VNC = VCOM = 0V, ISL84541/2/3 f = 1MHz, VNO or VNC = VCOM = 0V, ISL84544 POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, all channels on or off
25 25
-
13 20
-
pF pF
Full
-1
-
1
A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full Full Full 2.4 -1 0.8 1 V V A
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ISL84541, ISL84542, ISL84543, ISL84544 Test Circuits and Waveforms
3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 1k CL 35pF VOUT tr < 20ns tf < 20ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON VG GND IN CL
LOGIC INPUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
3V LOGIC INPUT 0V VNX SWITCH OUTPUT VOUT1 90% 0V
FIGURE 2B. TEST CIRCUIT
V+
C
NO1
VOUT1 COM1 VOUT2 RL1 300 CL1 35pF
NC2
COM2 IN1 RL2 300
SWITCH OUTPUT VOUT2
90% 0V LOGIC INPUT
IN2 GND
CL2 35pF
tD
tD
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS (ISL84543 ONLY) FIGURE 3B. TEST CIRCUIT (ISL84543 ONLY)
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ISL84541, ISL84542, ISL84543, ISL84544 Test Circuits and Waveforms (Continued)
V+ 3V LOGIC INPUT 0V VNX
NO
C
COM
NC
VOUT RL 300 CL 35pF
SWITCH OUTPUT VOUT
90% 0V tD LOGIC INPUT
IN GND
CL includes fixture and stray capacitance. FIGURE 3C. MEASUREMENT POINTS (ISL84544 ONLY) FIGURE 3D. TEST CIRCUIT (ISL84544 ONLY)
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+ C SIGNAL GENERATOR RON = V1/1mA
NO or NC NO or NC
V+ C
VNX INX 0V or 2.4V 1mA V1 IN 0.8V or 2.4V
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO1 or NC1 COM1
50
NO or NC
IN1 0V or 2.4V IN2 0V or 2.4V INX IMPEDANCE ANALYZER
COM
0V or 2.4V
ANALYZER RL
COM2
NO2 or NC2
GND
NC
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
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ISL84541, ISL84542, ISL84543, ISL84544 Detailed Description
The ISL84541-ISL84544 dual analog switches offer precise switching capability from a single 2.7V to 12V supply with low on-resistance (30) and high speed operation (tON = 35ns, tOFF = 25ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (5W), low leakage currents (100pA max), and the tiny SOT-23 packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL8454X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
Logic-Level Thresholds
This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 15). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 300MHz (see Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, off isolation is about 50dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM
GND OPTIONAL PROTECTION DIODE
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced,
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8454X construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set 9
ISL84541, ISL84542, ISL84543, ISL84544
they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V+ or GND.
Typical Performance Curves TA = 25oC, Unless Otherwise Specified
40 35 30 85oC RON () 25 RON () 20 15 10 5 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 25oC -40oC 45 40 35 30 25 20 15 30 25 20 15 10 20 15 10 5 0 -40oC 2 4 6 VCOM (V) 8 10 12 85oC 85oC 25oC -40oC V+ = 5V 85oC 25oC -40oC 25oC V+ = 12V V+ = 3.3V
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
0.5 0.4 0.3 0.2 0.1 0 0.25 0.2 0.15 0.1 0.05 0 0.15 0.1 0.05 0 0
V+ = 3.3V 25oC
60 50
85oC
-40oC V+ = 5V
40 30 Q (pC) 20 10 -40oC 0 25oC V+ = 12V 25oC 10 12 -10 -20 0 2 4 6 VCOM (V) 8 10 12 V+ = 3.3V V+ = 5V V+ = 12V
RON ()
25oC 85oC
85oC
-40oC
85oC -40oC 2 4 6 VCOM (V) 8
FIGURE 11. RON MATCH vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
10
ISL84541, ISL84542, ISL84543, ISL84544 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
100 90 80 70 tON (ns) 60 85oC 50 -40oC 40 30 25oC 20 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 15 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40oC 20 25oC 30 85oC tOFF (ns) 35
25 -40oC
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
3.0
V+ = 3.3V to 12V 0 -3 -6 PHASE 0 20 PHASE (DEGREES) GAIN
2.5 VINH VINH AND VINL (V) 2.0 -40oC 85oC
1.5
25oC -40oC
85oC
40 60
1.0 VINL 85oC 0.5 2 3 4 5 6 7 8 V+ (V) 9 10
25oC
RL = 50 VIN = 0.2VP-P to 2.5VP-P (V+ = 3.3V) VIN = 0.2VP-P to 4VP-P (V+ = 5V) VIN = 0.2VP-P to 5VP-P (V+ = 12V) 12 13 1 10 100 FREQUENCY (MHz)
80 100 600
11
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 16. FREQUENCY RESPONSE
-10 V+ = 3V to 13V -20 -30 -40 CROSSTALK (dB) -50 -60 -70 -80 -90 CROSSTALK -100 -110 1k ISOLATION
10 20 30 OFF ISOLATION (dB) 40 50 60 70 80 90 100 110 100M 500M
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ISL84541: 66 ISL84542: 66 ISL84543: 66 ISL84544: 58 PROCESS: Si Gate CMOS
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 17. CROSSTALK AND OFF ISOLATION
11
ISL84541, ISL84542, ISL84543, ISL84544 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
12
ISL84541, ISL84542, ISL84543, ISL84544 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
4X L L1
e E L
0.026 BSC 0.187 0.016 0.199 0.028
0.65 BSC 4.75 0.40 5.05 0.70
A
A2
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 8 0.003 0.003 5o 0o 15o 6o
0.95 REF 8 0.07 0.07 5o 0o
C a C L E1
C
R1 0
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
13
ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
14
ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Transistor Plastic Packages (SOT23-6)
0.20 (0.008) M C L b e C VIEW C
P6.064
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL MIN 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060 MAX 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.068 MILLIMETERS MIN 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.75 6 6 3 3 4 NOTES -
6 C L 1
5
4 C L E E1
A A1 A2 b b1
2
3
e1 C D C L
c c1 D E E1
SEATING PLANE -C-
A
A2
A1
e e1 L
0.0374 Ref 0.0748 Ref 0.014 0.022
0.95 Ref 1.90 Ref 0.35 0.55
0.10 (0.004) C
L1 L2
0.024 Ref. 0.010 Ref. 6 0.004 0.004 0o 0.010 8o
0.60 Ref. 0.25 Ref. 6 0.10 0.10 0o 0.25 8o Rev. 3 9/03 5
WITH PLATING c
b b1 c1
N R R1
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
4X 1 R1 R GAUGE PLANE SEATING PLANE C L1 4X 1 VIEW C L
2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
15
ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Transistor Plastic Packages (SOT23-8)
0.20 (0.008) M C L b C
P8.064
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL A MIN 0.036 0.000 0.036 0.009 0.009 0.003 0.003 0.111 0.103 0.060 MAX 0.057 0.0059 0.051 0.015 0.013 0.009 0.008 0.118 0.118 0.067 MILLIMETERS MIN 0.90 0.00 0.90 0.22 0.22 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.38 0.33 0.22 0.20 3.00 3.00 1.70 6 6 3 3 4 NOTES -
e
8 C L 1
7
6
5 E C L E1
A1 A2 b
2
3
4
b1 c e1
D C L C
c1 D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0768 Ref 0.014 0.022
0.65 Ref 1.95 Ref 0.35 0.55
0.024 Ref. 0.010 Ref. 8 0.004 0.004 0o 0.010 8o
0.60 Ref. 0.25 Ref. 8 0.10 0.10 0o 0.25 8o Rev. 2 9/03 5
0.10 (0.004) C
L2 N
WITH PLATING c
b b1 c1
R R1
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178BA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE C L1 4X 1 VIEW C L
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
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